[Libre-soc-bugs] [Bug 324] create POWER DIV pipeline

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Thu Jul 2 21:01:03 BST 2020


--- Comment #50 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #45)
> (In reply to Luke Kenneth Casson Leighton from comment #42)
> > btw several combinatorial stages chained together is absolutely fine
> > as long as it's not too many.  i'm going to try 8 (it's a 180nm ASIC)
> Seems excessive since then there would be a gate depth of on the order of
> 100 per pipeline stage, I seriously doubt we can get any decent clock speed
> from something *that* deep.

yehh i don't honestly know, should be running ltp to find out
(which is currently having a hard time with the number of register
"loops" detected...)

You are receiving this mail because:
You are on the CC list for the bug.

More information about the libre-soc-bugs mailing list