[Libre-soc-bugs] [Bug 324] create POWER DIV pipeline

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Thu Jul 2 20:55:39 BST 2020


--- Comment #48 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #44)
> (In reply to Luke Kenneth Casson Leighton from comment #41)
> > btw jacob i noticed that on qemu, divw sets RT=RA when RB=0.
> > 
> > can you check that behaviour on POWER9?
> IIRC, on POWER9, division by zero results in RT=0 for all div*/mod*
> instructions. I specifically included that as a test case in
> power-instruction-analyzer since that's a case where the result is undefined
> according to the PowerISA spec. For divwo, see:
> https://salsa.debian.org/Kazan-team/power-instruction-analyzer/-/blob/
> 13dae100c6bc5685059195010ceb46ae68b9f306/src/instr_models.rs#L153

qemu definitely sets RT=RA for divw when RB=0.  note: not divwo - *divw*.

which is why i asked if you could check.  hugh and paul mackerras mentioned
that this *might* have been old behaviour on e.g. POWER7 or POWER8.

if you run the unit test simulator/test_div_sim.py (and edit it
accordingly) you will be able to see for yourself.

FAIL: test_0_divw (__main__.DivZeroDecoderTestCase)
Traceback (most recent call last):
  File "simulator/test_div_sim.py", line 80, in test_0_divw
    self.run_tst_program(program, [1, 2, 3])
  File "/home/lkcl/src/libresoc/soc/src/soc/simulator/test_sim.py", line 252,
in run_tst_program
    self.qemu_register_compare(simulator, q, reglist)
  File "/home/lkcl/src/libresoc/soc/src/soc/simulator/test_sim.py", line 290,
in qemu_register_compare
    self.assertEqual(qemu_val, sim_val)
AssertionError: 22136 != 0

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