[Libre-soc-bugs] [Bug 230] Video opcode development and discussion

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=230

--- Comment #55 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to cand from comment #51)
> Since we only do up to vec4, the variable widths can be encoded in a 16-bit
> immediate, 4-4-4-4, if limited to <= 16. Alternatively a 32-bit immediate
> would allow the full 64 range.

ok i am glad you said this: we don't have space in the ISA for 16 bit
immediates.  6 bits EXTNNN, 16 bits imm that's 22.  only 10 bits remain that's
enough for 2x 5bit regs, but an *entire* precious Major Opcode was taken up.

want another op, take another Major Op.

32 bit immediates unfortunately require a 64 bit instruction and there is no
(sane) way to include SV on top of that.  or, there might be but i don't want
to explore that rabbithole unless we are forced to.

-- 
You are receiving this mail because:
You are on the CC list for the bug.