[Libre-soc-bugs] [Bug 373] Investigate the possibility of implementing parts of OPENCAPI to supplement Wisbone vB4

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=373

Jacob Lifshay <programmerjake at gmail.com> changed:

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                 CC|                            |programmerjake at gmail.com

--- Comment #3 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #2)
> 25ghz external clock requires an internal 50 ghz stable PLL, which is 14nm
> territory.

I don't think that's actually true, all you need is a 25GHz PLL with a approx.
50% duty cycle and to use both negative and positive edge-triggered flip flops.

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