[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=305

--- Comment #29 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/alu/main_stage.py;hb=HEAD#l137

i'm fairly certain that this:

 136             with m.Case(InternalOp.OP_RLC):
 137                 with m.If(self.i.ctx.op.imm_data.imm_ok):
 138                     comb += rotate_amt.eq(self.i.ctx.op.imm_data.imm[0:5])
 139                 with m.Else():
 140                     comb += rotate_amt.eq(self.i.b[0:5])

can just be this:

 136             with m.Case(InternalOp.OP_RLC):
 137                 comb += rotate_amt.eq(self.i.b[0:5])

because in input_stage.py there is this:

  40         # If there's an immediate, set the B operand to that
  41         with m.If(self.i.ctx.op.imm_data.imm_ok):
  42             comb += self.o.b.eq(self.i.ctx.op.imm_data.imm)
  43         with m.Else():
  44             comb += self.o.b.eq(self.i.b)

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