[libre-riscv-dev] [Bug 270] New: investigate nmigen clock gating

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=270

            Bug ID: 270
           Summary: investigate nmigen clock gating
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Source Code
          Assignee: lkcl at lkcl.net
          Reporter: lkcl at lkcl.net
                CC: libre-riscv-dev at lists.libre-riscv.org
   NLnet milestone: ---

see
http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-March/005482.html

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