[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

--- Comment #127 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
oh - i just spotted this in p30, section 2.3.1.  it seems to concur with
ppc_update_cr0 *except* of course, it's been adapted for 32/64-bit modes.

if (64-bit mode)
   then M <= 0
   else M <= 32
if       (target_register)[M:63] < 0 then c <= 0b100  # bit 31
else if (target_register)[M:63] > 0 then c <= 0b010   # bit 30
else                                      c <= 0b001  # bit 29
CR0 <= c || XERSO                                     # bit 28

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