[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

--- Comment #125 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Michael Nolan from comment #124)
> (In reply to Luke Kenneth Casson Leighton from comment #122)
> 
> > how many bits is that
> > 0x 1 0000 0000 0000 4444
> > 
> > ha, that's amusing.  the result is a roll-over from 64-bit arithmetic
> > 
> > > Need to sort out setting the carry and overflow flags at some
> > > point though, that'll be more fun...
> > 
> > yehyeh.  a SPR storing the carry, first.  take a look at pearpc,
> > it should show a way to do it (that's easy to interpret)
> > https://github.com/sebastianbiallas/pearpc
> 
> Ooops, some of my experiments with carry must have snuck in, sorry. 

no worries

> Speaking
> of, I'm getting some weird behavior with carry on qemu. If I run some
> instructions that generate a carry or overflow, then have gdb read the xer
> register, it returns 0. But if I execute a `mfxer r5` or the like and print
> out that register, it gives me the correct value for xer. I'm trying to
> confirm whether this is a bug with qemu or not.

hmmm.  if it's a bug in qemu it's one that, i suspect, would have been detected
a loooong time ago.  but... you never know...

let's look at the spec:

p70 3.0B "addc":

RT <= (RA) + (RB)

The sum (RA) + (RB) is placed into register RT.
Special Registers Altered:
    CA CA32
    CR0                                       (if Rc=1)
    SO OV OV32                               (if OE=1)

ok so SO (summary overflow), OV (overflow) and OV32 (overflow 32-bit)
all get set, in XER.  these are listed on p45 3.2.2

however that's not the "carry" flag: that's *CR0*.  which is in... errr...
the Condition Register p45 2.3.1

let's check the pearpc source (yes it's only 32-bit).  ppc_alu.c
whereisitwhereisit...  ok!

https://github.com/sebastianbiallas/pearpc/blob/master/src/cpu/cpu_generic/ppc_alu.cc#L56

ahh, then as a *separate* concern, if you see the implementation of addcx,
that updatex XER_CA *and* updates CR0:
https://github.com/sebastianbiallas/pearpc/blob/master/src/cpu/cpu_generic/ppc_alu.cc#L86

-- 
You are receiving this mail because:
You are on the CC list for the bug.