[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

--- Comment #85 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
line 32
for t in range(lenself - stop - 1, lenself - start - 1)

except this is wrong because bits are not stepped properly


so it is probably

l = list(range(start, stop, step)
l = l.reverse() # probably
for t in l:
   t = len(self) - t - 1
   carry on

for the else bit just do the t sub-from-self before lookup, too

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