[libre-riscv-dev] [Bug 206] Implement branch prediction

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=206

--- Comment #19 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://github.com/patc15/mipscpu/blob/master/branch_history_table.v#L101

is this code (the block at line 101) *undoing* a miapredicted branch?

that means the SRAM has to be dual-ported, and if we do dual-issue it'll be
*quad* ported.

eek

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