[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=325

--- Comment #76 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
i'm also attempting to add support for TRAP - as a function - in the
parser and simulator, *without* changing fixedtrap.mdwn, which is
taken directly from the 3.0B PDF.  bit of a pain.

now, if you create a test_tdi() function in trap test_pipe_caller.py,
the simulator *should* print out "TRAP TODO".


diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index 61aa451..ae5d479 100644
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -233,6 +233,11 @@ class ISACaller:
         self.decoder = decoder2.dec
         self.dec2 = decoder2

+    def TRAP(self, trap_addr=0x700):
+        print ("TRAP: TODO")
+        # store PC in SRR0, set PC to 0x700
+        # store MSR in SRR1, set MSR to um errr something
+
     def memassign(self, ea, sz, val):
         self.mem.memassign(ea, sz, val)

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