[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=325

--- Comment #45 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
 184                     with m.If(a[MSR_PR]):
 185                             msr_o[MSR_EE].eq(1)
 186                             msr_o[MSR_IR].eq(1)
 187                             msr_o[MSR_DR].eq(1)

should be msr_o.data

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