[libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=313

--- Comment #47 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Michael Nolan from comment #46)
> (In reply to Luke Kenneth Casson Leighton from comment #44)
> 
> > bear in mind that DecodeA reads CTR, (which goes into read_fast1)
> > and DecodeB reads LR or TAR (which goes into read_fast2).
> > 
> > so the above test needs to be split.
> 
> So main_stage.py will need to check whether the instruction is a bcctr and
> use spr1, otherwise use spr2?

sigh yes.  although what i was going to do was to just make BCREG use spr2
for CTR/LR/TAR and BC uses spr1=CTR.

i believe that may end up being simpler, because main_stage.py would not
need to decode XO[5/9]?

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