[libre-riscv-dev] daily kan-ban update, 22jul2020

Luke Kenneth Casson Leighton lkcl at lkcl.net
Thu Jul 23 03:29:47 BST 2020

On Thursday, July 23, 2020, Jacob Lifshay <programmerjake at gmail.com> wrote:

> today:
> still working on Div FSM -- I think it's complete (except for not
> supporting cancellation), but didn't thoroughly test it yet. In the
> process of refactoring test_pipe_caller.py into a easier-to-test shape
> and adding parallel test cases for DivPipeCore, FSMDivCore, and
> SimOnly, I discovered that for test_divwuo_regression_1 (0xc4e32b68 /
> 0x32867d69), the pipeline (SimOnly) is giving the correct results
> (rt=0x3), it's the ISA simulator code that's messed up
> (rt=0xFFFFFFFF).

please raise a bugreport for it.

> Luke (or whoever is more familiar with it), I'll let you figure out
> how to fix the ISA simulator.

it's running the pseudocode.  if the pseudocode gives the wrong answer,
that's bad.

what happens when testing the same values in simulator/test_div_dim.py?

hm wait you can't put initial regs into qemu yet.  been meaning to add that.


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