[libre-riscv-dev] go die/cancel signals in fsm

Luke Kenneth Casson Leighton lkcl at lkcl.net
Wed Jul 22 13:27:39 BST 2020

On Wed, Jul 22, 2020 at 10:51 AM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:

> > This is
> > needed to not have to wait 63(!) more clock cycles for a canceled div
> > instruction to finish computing before another div instruction can be
> > started.
> indeed.

for now, you can see that issuer.py is a FSM:

so there's not going to be any cancellation.  instructions are done
one at a time, total freeze until the instruction is completed.


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