[libre-riscv-dev] go die/cancel signals in fsm

Jacob Lifshay programmerjake at gmail.com
Wed Jul 22 03:01:36 BST 2020

I looked through the vcd generated for soc.simple.test.test_core and
was unable to locate the signals used to tell the pipeline stages that
the instruction they are currently operating on is canceled. This is
needed to not have to wait 63(!) more clock cycles for a canceled div
instruction to finish computing before another div instruction can be

Help wanted,

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