[libre-riscv-dev] daily kan-ban update 19jul2020
yimmanuel3 at gatech.edu
Sun Jul 19 22:38:08 BST 2020
> i have no idea if verilator generates vcd files which would allow debugging
> if there are issues (instructions missing for example)
Verilator does generate VCDs…
LiteX abstracts that away for you, however,
I will say that its a pretty painful process
to run through LiteX generated VCds.
They are flattened as oMigen outputs flat verilog.
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