[libre-riscv-dev] daily kan-ban update 17jul2020
programmerjake at gmail.com
Sun Jul 19 08:04:05 BST 2020
On Fri, Jul 17, 2020, 20:37 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> On Saturday, July 18, 2020, Jacob Lifshay <programmerjake at gmail.com>
> > today:
> > started adding fsm div
> > got a test where a whole bunch of the core fsm transition functions
> > are strung together combinatorially to work
> > (soc.fu.div.test.test_fsm.TestDivState.test_div_state_comb), so that
> > means that the soc.fu.div.fsm.DivState* classes all work.
> > However, when I try to wire them up in a simple synchronous fsm
> > (soc.fu.div.test.test_fsm.TestDivState.test_div_state_fsm), it doesn't
> > seem to work: I think the simulation process I made that checks
> > outputs is somehow getting desynchronized from the process that
> > toggles inputs -- I added some extra wires that the check process
> > toggles.
> ah. we learned that even for synchronous signals it can be necessary to
> use Settle().
> this usually when a combinatorial block is generated *from* a synchronous
I'm specifically using Delay to delay a fraction of a clock cycle after
each Tick before measuring values, so Settle shouldn't be necessary.
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