[libre-riscv-dev] daily kan-ban update 17jul2020

Jacob Lifshay programmerjake at gmail.com
Sat Jul 18 04:27:20 BST 2020

started adding fsm div
got a test where a whole bunch of the core fsm transition functions
are strung together combinatorially to work
(soc.fu.div.test.test_fsm.TestDivState.test_div_state_comb), so that
means that the soc.fu.div.fsm.DivState* classes all work.

However, when I try to wire them up in a simple synchronous fsm
(soc.fu.div.test.test_fsm.TestDivState.test_div_state_fsm), it doesn't
seem to work: I think the simulation process I made that checks
outputs is somehow getting desynchronized from the process that
toggles inputs -- I added some extra wires that the check process
toggles. it appears to me as though the check process is somehow
delayed an entire divide operation (8 or 9 cycles, since I'm testing
an 8-bit divider to make it easier).

Will try to fix that after tomorrow


More information about the libre-riscv-dev mailing list