[libre-riscv-dev] bisecting nmigen

Luke Kenneth Casson Leighton lkcl at lkcl.net
Sat Jul 11 12:34:43 BST 2020

commit 2606ee33ad548bed1b9294bbca3962e834d12fd0
Author: whitequark <whitequark at whitequark.org>
Date:   Sun Jun 28 05:04:16 2020 +0000

    back.pysim: simplify.

    Remove _EvalContext, which was a level of indirection serving almost
    no purpose. (The only case where it would be useful is repeatedly

turns out it does serve a purpose: the div simulation hasn't completed
in 10 minutes, where it normally takes... maybe... 25 seconds?  i've
stopped it running.

commit 6d417568ad68565fc7e01e7611ce8cf0b8fdb603
Author: whitequark <whitequark at whitequark.org>
Date:   Wed Jul 8 08:29:20 2020 +0000

    back.pysim: only extract signal names if VCD is requested.

    This commit also fixes an issue introduced in 2606ee33 that regressed
    simulator startup time and bloated VCD files. (It's actually about
    10% faster now than *before* the regression was introduced.)

it's not complete.  i ran a diff on the vcd files: it looks to me like
it's actually dumping zeros into the vcd file.  as in: *actual* zero
values are being outputted.  in other words there's nothing wrong
*with the vcd file itself*: nmigen has *outputted zeros* into a VCD
file that is correctly and legally formatted.

in the meantime whilst that's being sorted, it is necessary to use
this git revision:

commit 303ea18cb60567e45a755c6b6289a601f27d46e6 (HEAD, tag: working2)
Author: Alan Green <alan.green at gmail.com>
Date:   Tue Jun 23 22:12:02 2020 +1000

    _yosys: handle unparseable versions


More information about the libre-riscv-dev mailing list