[libre-riscv-dev] daily kan-ban update 09jul2020
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Fri Jul 10 18:25:40 BST 2020
On Friday, July 10, 2020, Jacob Lifshay <programmerjake at gmail.com> wrote:
> yes, I know and expected that. I'll repeat myself until you get that I was
> looking at the ra and rb *inputs* in *this stage* as well as the previous
> stage. those *inputs at the beginning of the pipeline* were zero.
ok am with you. that's very odd, because when i added those lines the
correct expected values propagated down the whole thing.
sorry had to narrow down by being able to say what it wasn't :)
there is actually a word for this in vedic epistemology (advaita vedanta)
which is "knowledge by difference". the discrepancy in a comparison *is*
took a couple of rounds to get there though :)
> plus, given that the break in the pipeline has been
> > identified i don't believe it necessary to raise the bugreport.
> it *is* necessary to report (unless fixed meanwhile), since you got
> distracted by the wrong thing and completely missed that the signals that
> shouldn't have been zero since they *are* connected to the pipeline inputs
> -- those signals *are* zero in the vcd file.
yes with you now. sorry took a while.
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