[libre-riscv-dev] daily kan-ban update 09jul2020

Luke Kenneth Casson Leighton lkcl at lkcl.net
Fri Jul 10 10:05:53 BST 2020

On Fri, Jul 10, 2020 at 8:45 AM Jacob Lifshay <programmerjake at gmail.com> wrote:
> On Thu, Jul 9, 2020 at 7:10 PM Luke Kenneth Casson Leighton
> <lkcl at lkcl.net> wrote:
> >
> > On Friday, July 10, 2020, Jacob Lifshay <programmerjake at gmail.com> wrote:
> >
> > > today:
> > > attended the OpenPower virtual coffee meeting
> > > Luke found a bug in the div pipeline, I was able to reproduce it, but
> > > the VCD file nmigen produced was utterly useless -- nearly everything
> > > is set to 0. Luke (or someone else), I need help here.
> >
> >
> >  i got that too, gtkwave is known to not always display everything
> > correctly.
> I checked with a completely independent vcd reader and gtkwave is not
> at fault this time. nmigen really did write a messed up file.

ok then that's best raised as a bugreport.

btw before doing that i suggest examining the yosys graphviz (show
{modulename}).  i just noted for example that ra$1 (etc) are not
connected yet are passed into pipe_N_to_N, then passed in to
core_calculate_stage_N, then *still* not used.

this because of the inheritance tree DivCoreCalculateStage -> Base,
CoreBaseData inheriting from DIVInputData, DIVInputData contains ra,
rb, xer_so.

so whilst it's correct that xer_so should be propagated right the way
through the pipeline (for sticky-overflow processing *right* at the
end - sigh) - ra and rb are not necessary and are thrown away.

> The vcd reader I used is: https://github.com/sgpthomas/vcdump/pull/1
> > honestly if we spend much more time on this it's time instead to convert
> > microwatt DIV FSM to nmigen.
> Yeah, though with the way that nmigen and/or the pipeline is messed
> up, we're highly likely to run into this problem on any new code too.

there's nothing wrong with the simulation / pipeline: it's the
calculation of overflow.  it's real simple to check: delete these

        # check 32/64 bit version of overflow
        with m.If(op.is_32bit):
            calc_overflow(self.i.dive_abs_ov32, 0x80000000)
        with m.Else():
            calc_overflow(self.i.dive_abs_ov64, 0x8000000000000000)

if deleted, answer to test_6_regression equals correct.


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