[libre-riscv-dev] 130nm for the hackers : finally a reality ?
staf at fibraservi.eu
Fri Jul 3 14:48:55 BST 2020
Luke Kenneth Casson Leighton schreef op vr 03-07-2020 om 13:55 [+0100]:
> in *theory* then it would be possible to connect up the peripheralsdirectly and bypass parts of litex. however looking at quite how muchlitex actually does:https://github.com/enjoy-digital/litex/blob/master/litex/soc/integration/soc.py
> that's what would be need to be rewritten - replaced - with somethingthat links up all the peripherals (in nmigen). and that's a _lot_ ofwork.
Nono, one would still use soc.py as it is just add a platform that spits out a verilog file of the whole soc top and not call the FPGA tool chain for synthesis and P&R.
This top verilog would then be used through Instance in nmigen and combined with IO and go through Coriolis flow.
More information about the libre-riscv-dev