[libre-riscv-dev] 130nm for the hackers : finally a reality ?
staf at fibraservi.eu
Thu Jul 2 14:47:06 BST 2020
Luke Kenneth Casson Leighton schreef op do 02-07-2020 om 13:27 [+0100]:
> On Thu, Jul 2, 2020 at 12:04 PM Staf Verhaegen <staf at fibraservi.eu> wrote:
> > Is there already a design with mixed litex and nmigen code ?If so, it would save me from reinventing the wheel for the Retro-uC.
> i've been looking for one: what i've found so far is this:https://git.m-labs.hk/M-Labs/HeavyX/src/branch/master/examples/simplesoc_ecp5.py
> litex however is migen (legacy), and my feeling is that to get it toproperly work you need to "back down" to a common denominator, whichis convert everything to verilog (or ilang) and, if doing simulations,run verilator (or now cxxrtl).
Well aware of that, therefor my question.
> in other words i believe in order to use litex you kinda have to treatnmigen as a foreign architecture (vhdl, verilog) just like it's donewith any other soc such as microwatt, vexrisc and so on.
I would like to go to other way: having litex peripherals as external source in nmigen top. Reason is that I do plan to use the nmigen Platform for defining the IOs etc; also for the 0.18um prototype.
More information about the libre-riscv-dev