[libre-riscv-dev] building a simple barrel processor

Jacob Lifshay programmerjake at gmail.com
Sat Mar 30 00:28:56 GMT 2019

> i do not believe that such a proposal, for general-purpose usage in
> the year 2019, would ever be taken seriously.  as in: i can't possibly
> go back to the client / sponsor and say that we're going to do a
> processor design that's only capable of 200mhz single-threaded
> execution.
> he'd tell me that he'll go use a 4-SMP rocket-chip, which has been
> silicon-proven to do 1.5ghz a number of times, and he'll license
> Vivante's GC800 3D engine for USD $250,000.
Yeah, makes sense. I'd probably make the same decision.

> can you clarify?
Yeah, a barrel processor by definition follows strict round robin, so each
thread effectively runs at 1/Nth of the clock frequency of the whole
processor, even if all but 1 of the threads are sleeping.

My proposal for increasing performance when single-threaded programs need
higher speed is to create a hybrid design between a barrel processor and a
simple RISC processor (so, not only a barrel processor) by overlaying on
the barrel processor's pipeline a simple RISC pipeline, such that the
pipeline is used as a barrel processor, or the pipeline can be switched to
a single-issue, in-order RISC processor, effectively putting all other
harts to sleep while in single-threaded mode. The single threaded mode
would be activated when all other harts on the same barrel processor core
are sleeping. Notably, the single-threaded mode doesn't need to implement
all instructions since we can just switch the processor back to barrel mode
to execute the unimplemented instructions. That then allows us to make the
single-threaded pipeline much simpler (eg. not implementing anything
outside of RV64GC, allowing us to only need a 64-bit datapath and a
31-register 2R1W integer register file and a 32-register 3r1w fp register
file. The single-threaded register files would logically be the lower
registers of hart #0's register file even in barrel mode, allowing us to
not need to copy between register files when switching modes.


More information about the libre-riscv-dev mailing list