[libre-riscv-dev] multi-in. multi-out pipeline
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Wed Mar 27 21:51:26 GMT 2019
ok! this is a 4-in mux, 2 passthrough, 4-fanout pipeline, where the
fan-in and fan-out are combinatorial and the passthrough stages in the
middle are clock-sync'd.
this basically constitutes the bedrock of the "Concurrent Computation
Unit" that was mentioned a few weeks ago.
* the 4-in mux allows 4 sets of input operands (Reservation Stations)
to wait for the pipeline to be ready. the mux ID goes into the pipe
as part of the data
* the 2 sync'd stages are where the IEEE754 FPU would go. mux ID gets
* the 4-fanout receives the data and the mux id, and fans out the
result to the correctly-matching Reservation Station.
it was quite straightforward to do, by combining the in-mux unit test
with the out-mux unit test. the data is sent in "priority" order
(because that's the input arbiter currently available), and correctly
re-assembles out the other side.
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