[libre-riscv-dev] TLB key for CAM
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Wed Mar 27 10:30:43 GMT 2019
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On Wed, Mar 27, 2019 at 7:27 AM Jacob Lifshay <programmerjake at gmail.com> wrote:
> On Wed, Mar 27, 2019, 00:17 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> > except, where the first level TLB comes from the L1 cache of one SMP
> > core, the second level TLB would have *multiple* cores so a 4-way bus
> > (we're aiming for 4 cores) and only the one L2 cache (with the same
> > 4-way bus to/from all 4 cores).
> There's a problem with sharing the L2 TLB between cores: the RISC-V
> priveleged spec specifies that the page tables of each core are
> independently settable and that ASIDs are not necessarily shared between
> cores, which implies that a TLB entry from one core would be totally
> useless to the other cores and we would be better off with per-core L2
> TLBs. That would also make the L2 TLB logic much simpler.
oh ok! good catch.
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