[libre-riscv-dev] buffered pipeline

Luke Kenneth Casson Leighton lkcl at lkcl.net
Sat Mar 23 06:29:59 GMT 2019

this works, jacob: i took a look at the unit test test_simulation.py

(btw can i recommend using run_simulation, it does exactly the same job?)

key differences:

* moved the explicit combinatorial setting of the ports outside to a
time-sync'd setup
* removed the "synchronous=False" argument
* set the write-enable to zero *AFTER* writing
* then set the read address

this now passes.

* setting "sychronous=False" causes a failure
* setting the read address early causes a failure
* failing to set the write-enable back to zero causes a failure
* failing to allow the clock to run for one cycle where write-enable
is high causes a failure

i'm trying some other experiments (which are failing).


from nmigen import Module, Memory
from nmigen.compat.sim import run_simulation

import unittest

class TestMemory(unittest.TestCase):
    def test(self) -> None:
        class TestModule:
            def __init__(self):
                self.mem = Memory(8, 16, name="mem", init=[0, 0])
                self.mem_rd0 = self.mem.read_port()
                self.mem_rd1 = self.mem.read_port()
                self.mem_wr0 = self.mem.write_port(priority=0)
                self.mem_wr1 = self.mem.write_port(priority=1)

            def elaborate(self, platform):
                m = Module()
                m.submodules.mem_rd0 = self.mem_rd0
                m.submodules.mem_rd1 = self.mem_rd1
                m.submodules.mem_wr0 = self.mem_wr0
                m.submodules.mem_wr1 = self.mem_wr1
                return m
        module = TestModule()

        def async_process(module):
            self.assertEqual((yield module.mem_rd0.data), 0)
            self.assertEqual((yield module.mem_rd1.data), 0)
            yield module.mem_wr0.addr.eq(0)
            yield module.mem_wr0.data.eq(1)
            yield module.mem_wr0.en.eq(1)
            yield module.mem_wr1.addr.eq(1)
            yield module.mem_wr1.data.eq(1)
            yield module.mem_wr1.en.eq(1)
            yield module.mem_wr0.en.eq(0)
            yield module.mem_wr1.en.eq(0)
            yield module.mem_rd0.addr.eq(0)
            yield module.mem_rd1.addr.eq(1)
            self.assertEqual((yield module.mem_rd0.data), 1)
            self.assertEqual((yield module.mem_rd1.data), 1)

            #           ports=[module.mem_rd0.data,
            #                   module.mem_rd1.data],
                       vcd_name = "test.vcd")

On Sat, Mar 23, 2019 at 4:54 AM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:
> ---
> crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
> On Sat, Mar 23, 2019 at 1:10 AM Jacob Lifshay <programmerjake at gmail.com> wrote:
> >
> > On Fri, Mar 22, 2019 at 1:46 AM Jacob Lifshay <programmerjake at gmail.com>
> > wrote:
> >
> > > implemented rc4, but I'm getting a test failure, will debug in the morning
> > >
> > nmigen appears to not support simulation of memory with multiple write
> > ports: https://github.com/m-labs/nmigen/issues/47
> > no wonder my rc4 implementation was failing.
>  okaay, so we have our first candidate that would justify donations to
> the nmigen team.
>  can you back-port it to migen and see if that works?
> l.

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