[libre-riscv-dev] buffered pipeline

Jacob Lifshay programmerjake at gmail.com
Sat Mar 23 01:09:52 GMT 2019

On Fri, Mar 22, 2019 at 1:46 AM Jacob Lifshay <programmerjake at gmail.com>

> implemented rc4, but I'm getting a test failure, will debug in the morning
nmigen appears to not support simulation of memory with multiple write
ports: https://github.com/m-labs/nmigen/issues/47
no wonder my rc4 implementation was failing.

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