[libre-riscv-dev] buffered pipeline

Luke Kenneth Casson Leighton lkcl at lkcl.net
Wed Mar 20 11:24:43 GMT 2019

ok that works.

class ExampleBufPipeChain2(BufferedPipeline):
    """ connects two stages together as a *single* combinatorial stage.
    def __init__(self):
        stage1 = ExampleStageCls()
        stage2 = ExampleStageCls()
        combined = StageChain([stage1, stage2])
        BufferedPipeline.__init__(self, combined)

or, much more simply (without the class declaration), as one line:
b = BufferedPipeline([ExampleStageCls(), ExampleStageCls()].

can also be:
b = CombPipe([ExampleStageCls(), ExampleStageCls()].

and functionally there's no difference (and no change in the code of
the stages).

example stage class looks like this:

class ExampleStageCls:
    def ispec(self):        return Signal(16, name="example_input_signal")
    def ospec(self):        return Signal(16, name="example_output_signal")
    def process(self, i):
        return i + 1

forgot to attach the graphviz screenshot earlier.  first is of how the
names "example_xxxx_stage" are in the output (ilang or verilog),
second is showing the chain of the 2 example "add" stages.

so, just to be clear: there's no need for registers, no need for
explicit creation of intermediary temporaries, and no need for
explicit assignment to combinatorial blocks, to use the StageChain.

it can be used to chain Stages together that are based around classes,
Records, Signals or nmigen modules: it doesn't matter, as long as each
Stage conforms to the ispec/ospec/process/setup API.

*sigh* could really have done with this code about a month ago... never mind :)

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