[libre-riscv-dev] buffered pipeline

[Jacob Lifshay]

I'm in the midst of converting the pipeline stages I wrote to using Record.
I'm redesigning the pipeline stage classes so we have the following classes:

CombStage:
0-clock-cycle delay
combinatorial logic
logic in either of process callback passed into constructor or overridden
process method

RegStage:
1-clock-cycle delay
valid output comes from flip-flop

ReadyIsolatorStage:
0-clock-cycle delay
ready output comes from flip-flop

planning on adding:
stage that has multiple input ports & 1 output port that waits for all
inputs to be valid at same time then transfers all inputs to output:
SynchronousFanIn

stage that has multiple input ports & 1 output port that waits for any
input to valid then transfers inputs one at a time to output

stage that has 1 input port and multiple output ports that waits for all
outputs to be ready then transfers to all outputs simultaneously:
SynchronousFanOut

those classes should make it much easier to build a pipeline.

considering adding separate cancel inputs to classes that can store data.

currently working on logic in ReadyIsolatorStage

Jacob Lifshay