[libre-riscv-dev] buffered pipeline

Jacob Lifshay programmerjake at gmail.com
Tue Mar 19 01:31:14 GMT 2019

what do you think of the naming and structure used in

On Mon, Mar 18, 2019 at 5:02 PM Luke Kenneth Casson Leighton <lkcl at lkcl.net>

> On Mon, Mar 18, 2019 at 10:07 PM Jacob Lifshay <programmerjake at gmail.com>
> wrote:
> >
> > One thing I noticed in your implementation is that IOAckIn has all the
> > inputs and IOAckOut has all the outputs.
>  yes.  the naming "input" and "output" was incredibly confusing from
> the src/pipeline.py code as they should be prev and nxt (next is a
> keyword). or prev_stage and next_stage.
> > I personally think IOAck is not an
> > appropriate name since none of the signals are named ack anymore
>  good point.  don't know what to suggest.  based it on the chisel3
> library having the word "ack" in it.  any recommendations?
> > Additionally, I would organize the signals into a group from/to the prev
> > stage and a group from/to the next stage.
>  yeah, then the linkage is much easier (connect, below).  the naming
> prefixes which include all six pieces of information however i find
> essential.  if swapping so that prev/next is the grouping, the
> input/output definitely needs to also be preserved [as the inner,
> second prefix].
> so, i_valid and o_ready in PredControl, and o_valid and i_ready in
> NextControl.  what will then happen i think is that in the connect
> functions, the ins will be eq'd to the outs.
> l.
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