[libre-riscv-dev] buffered pipeline
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Wed Mar 13 08:37:24 GMT 2019
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
On Wed, Mar 13, 2019 at 8:14 AM Jacob Lifshay <programmerjake at gmail.com>
> On Wed, Mar 13, 2019, 00:49 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> > so that's no longer about stopping two sets of logic() block from being
> > created, it's about ensuring that the processing does not occur
> > unnecessarily (i.e. only when input is valid).
> > what do you think?
> In CMOS combinatorial logic, ignoring leakage, it uses power only when the
> logic levels change, so I'd have the registers on the input of the
> combinatorial logic keep the state from the previous clock cycle instead of
> going to 0.
More information about the libre-riscv-dev