[libre-riscv-dev] TLB key for CAM
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Wed Mar 13 05:13:50 GMT 2019
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
On Wed, Mar 13, 2019 at 4:58 AM Daniel Benusovich <
flyingmonkeys1996 at gmail.com> wrote:
> > the example is of a RegisterFile. i mention it because you created a
> > class called RegisterFile and it uses an Array rather than a Memory
> > class.
> > the reason for using the Memory class is because the Memory class is
> > specifically designed to map down to verilog arrays / array indices,
> > which in turn are fully and properly recognised by synthesis tools to
> > map to SRAMs and ported memory, both on ASIC tools as well as FPGA
> > synthesis tools.
> Makes sense to me. I will delete my existing RegisterFile and use a
> memory block instead. Should I use the RegisterFile from the example?
> It seems so nice.
if it works and does the job, go for it.
btw one other requirement: pass-through on the register file. i.e. the data
being written is available *immediately* - on the *same* clock cycle - if
i belieeeeve this is an option to the Memory class, it may be necessary to
check on freenode #m-labs IRC.
this feature, very interestingly, effectively makes a Register File an
"operand forwarding bus".
More information about the libre-riscv-dev