[libre-riscv-dev] number of stages just increased to 6 per pipe-stage

Jacob Lifshay programmerjake at gmail.com
Mon Jul 29 14:59:07 BST 2019


I think you're looking at the diff backwards by mistake. when i implemented
frsqrt, I switched it to cram everything into 2 pipeline stages as a
debugging aid. the commit I just made switches it to what we had agreed on
in the gflops thread: 2 calc stages per pipeline stage.
https://git.libre-riscv.org/?p=ieee754fpu.git;a=blobdiff;f=src/ieee754/fpdiv/pipeline.py;h=bcd99e26dddcffbf35aa6cfe75511312149022d8;hp=68d07eefdb4651cc2b961700f295eac727fbd6ed;hb=30a3d1e975cd3df7ea701fdf0fe3bd0ba0757d3e;hpb=7c44b247e63bdbe1121819b114efeb9b67e7f4a6

On Mon, Jul 29, 2019, 06:52 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
wrote:

> hi jacob,
>
> +        # TODO (depends on how many RS's we want)
> +        #n_comb_stages = width // (2 * log2_radix)  # 2 compute steps per
> stage
> +        n_comb_stages = 2  # FIXME: switch back
> +
>          fraction_width = fmt.fraction_width
>
>          # extra bits needed: guard + round
> @@ -172,8 +176,6 @@ class FPDIVMuxInOut(ReservationStations):
>          # the last stage
>          cfg = DivPipeCoreConfig(fmt.width, fraction_width, log2_radix)
>
> -        n_comb_stages = (cfg.n_stages + 1) // 2  # 2 compute steps per
> stage
> -
>          self.pspec.fpformat = fmt
>          self.pspec.n_comb_stages = n_comb_stages
>          self.pspec.core_config = cfg
>
>
> what that's done is, well, you can see in the FPDIV32 pipeline, from
> the attached: it's now *seven* combinatorial stages long (!!)
>
> the number of combinatorial stages sets the "safe limit" for the gate
> count.  if it's not a fixed quantity, then as the bitwidth increases,
> so will the number of combinatorial stages chained together into a
> single pipeline stage.
>
> so, for FPDIV32, because n_comb_stages is set to the total number of
> *required* stages divided by two, that will be *FOURTEEN*
> combinatorial blocks jammed into each pipeline stage.
>
> the change that you made specifies, by mistake, that the *entire
> pipeline* must be no bigger than 2 deep.
>
> l.
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