[libre-riscv-dev] div/mod algorithm written in python

[Luke Kenneth Casson Leighton]

that's interesting...

the only test(s) that fail are these:
======================================================================
FAIL: test_radix_8_RSqrt
(ieee754.div_rem_sqrt_rsqrt.test_algorithm.TestFixedUDivRemSqrtRSqrt)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/test_algorithm.py",
line 1077, in test_radix_8_RSqrt
    self.helper(3, Operation.RSqrtRem)
  File "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/test_algorithm.py",
line 1044, in helper
    log2_radix)
  File "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/test_algorithm.py",
line 1026, in handle_case
    self.assertEqual(obj.remainder, remainder)
AssertionError: 0 != 4


diff --git a/berkeley-softfloat-3 b/berkeley-softfloat-3
--- a/berkeley-softfloat-3
+++ b/berkeley-softfloat-3
@@ -1 +1 @@
-Subproject commit b64af41c3276f97f0e181920400ee056b9c88037
+Subproject commit b64af41c3276f97f0e181920400ee056b9c88037-dirty
diff --git a/src/ieee754/div_rem_sqrt_rsqrt/algorithm.py
b/src/ieee754/div_rem_sqrt_rsqrt/algorithm.py
index 84ea1d4..6ff731c 100644
--- a/src/ieee754/div_rem_sqrt_rsqrt/algorithm.py
+++ b/src/ieee754/div_rem_sqrt_rsqrt/algorithm.py
@@ -779,7 +779,7 @@ class FixedUDivRemSqrtRSqrt:
             self.compare_lhs = self.divisor_radicand << (fract_width * 2)
         else:
             assert operation is Operation.RSqrtRem
-            self.compare_lhs = 1 << (fract_width * 3)
+            self.compare_lhs = 1 << (fract_width * 2)
         self.compare_rhs = 0
         self.remainder = self.compare_lhs
         self.operation = operation
diff --git a/src/ieee754/div_rem_sqrt_rsqrt/core.py
b/src/ieee754/div_rem_sqrt_rsqrt/core.py
index b62a957..2904461 100644
--- a/src/ieee754/div_rem_sqrt_rsqrt/core.py
+++ b/src/ieee754/div_rem_sqrt_rsqrt/core.py
@@ -250,7 +250,7 @@ class DivPipeCoreSetupStage(Elaboratable):
                 self.i.divisor_radicand << (self.core_config.fract_width * 2))
         with m.Else():  # DivPipeCoreOperation.RSqrtRem
             m.d.comb += self.o.compare_lhs.eq(
-                1 << (self.core_config.fract_width * 3))
+                1 << (self.core_config.fract_width * 2))

         m.d.comb += self.o.compare_rhs.eq(0)
         m.d.comb += self.o.operation.eq(self.i.operation)
diff --git a/src/ieee754/div_rem_sqrt_rsqrt/test_algorithm.py
b/src/ieee754/div_rem_sqrt_rsqrt/test_algorithm.py
index 9200b3b..12b4916 100755
--- a/src/ieee754/div_rem_sqrt_rsqrt/test_algorithm.py
+++ b/src/ieee754/div_rem_sqrt_rsqrt/test_algorithm.py
@@ -922,7 +922,7 @@ class TestFixedUDivRemSqrtRSqrt(unittest.TestCase):
         else:
             assert operation is Operation.RSqrtRem
             self.assertEqual(obj.compare_lhs,
-                             1 << (fract_width * 3))
+                             1 << (fract_width * 2))
             self.assertEqual(obj.compare_rhs,
                              obj.quotient_root * obj.quotient_root
                              * obj.divisor_radicand)

On Thu, Jul 25, 2019 at 11:30 AM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:
>
> btw if you're looking at that one, jacob, i'm going to go back to
> FCVT.  i'm also declaring fsqrt "done".
> l.