[libre-riscv-dev] div/mod algorithm written in python

[Luke Kenneth Casson Leighton]

 :attribute remainder: the remainder part of the result of the operation.
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        Signal with a bit-width of ``core_config.bit_width * 3`` and a
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        fract-width of ``core_config.fract_width * 3`` bits.
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    """
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    def __init__(self, core_config, reset_less=True):
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        """ Create a ``DivPipeCoreOutputData`` instance. """
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        self.core_config = core_config
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        self.quotient_root = Signal(core_config.bit_width,
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                                    reset_less=reset_less)
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        self.remainder = Signal(core_config.bit_width * 3,
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                                reset_less=reset_less)
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>
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Should be remainder = fract_width*3?

looks btw like for FPDIV, fract-width should be either zero or it should be
equal to bit_width. Nit sure which, yet. Both numbers are between 0.5 and
0.999999999 therefore i think it's fract_width=bit_width as the entire
number *is* fraction.

L.



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