[libre-riscv-dev] Introduction

[Jacob Lifshay]

sure

On Thu, Jan 31, 2019, 18:05 Luke Kenneth Casson Leighton <lkcl at lkcl.net
wrote:

> ---
> crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
>
> On Thu, Jan 31, 2019 at 9:15 PM Jacob Lifshay <programmerjake at gmail.com>
> wrote:
> >
> > just so you know, we're planning on a separate pipelined alu for
> > fdiv/fsqrt/frsqrt/idiv/irem that is possibly shared between 2 or 4 cores.
> >
> > I'm also planning on a unified ALU for i8/i16/i32/i64/f16/f32/f64 where
> the
> > alu is split into lanes with separate instructions for each 32-bit half.
> > So, the multiplier should be capable of 64-bit fmadd, 2x32-bit fmadd,
> > 4x16-bit fmadd, 1x32-bit fmadd + 2x16-bit fmadd (in either order), and
> all
> > (8/16/32/64) sizes of integer mul/mulhsu/mulh/mulhu in 2 groups of
> 32-bits.
> > We can implement fmul using fmadd with 0 (make sure that we get the right
> > sign bit for 0 for all rounding modes).
>
>  jacob could you add that to this page:
>  https://libre-riscv.org/3d_gpu/requirements_specification/
>
>  (you have access to it as a git repo gitolite3 at libre-riscv.org:
> libreriscv.git)
>
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