[libre-riscv-dev] spike-sv non-default element widths

[Luke Kenneth Casson Leighton]

something just occurred to me.  i was going to modify sext32 in spike
(i have an over-ride in place) so that when the bitwidth for source
elements are changed, sext32 could also change to sign-extend from
this:

#define sext32(x) (((sreg_t)(x) << (64-32)) >> (64-32))

to this:

#define sext_bwid(x,wid) (((sreg_t)(x) << (64-wid)) >> (64-wid))

where the default for wid would be 32, and any changes in bitwidth to
rs1 or rs2 would change wid to max(wid-rs1, wid-rs2).

i've since changed the definition of the SV elwidth field to this:

  switch (elwidth) {
      case 0: return xlen;
      case 1: return 8;
      case 2: return 16;
      default: return 32;
  }

now, the implications there are that when elwidth == 0, the default
behaviour for a W operation (addw) is that sext32 should be used:
WRITE_RD(sext32(rv_add(RS1, RS2)));

and, fascinatingly, for all *non* zero elwidths, the behaviour of
sext32 *still does not change*.

previously, i was considering changing sext32 because there was the
possibility of source operands being 64-bit or even 128-bit, and
that's no longer the case.

i think, realistically, it's probably best to leave the possibility of
larger elwidths to a future revision of SV, it makes things much much
easier.

did i miss anything?

l.