[libre-riscv-dev] New Person

[lkcl]

On Sun, Oct 14, 2018 at 8:30 AM lkcl <lkcl at libre-riscv.org> wrote:

> > Let me know what to work on next now that this is the correct result
> > (hopefully). I could work to fix the issue with the build folder or
> > whatever you need.

 the main immediate priority task is going to be unit tests, in
assembler, and writing macros (see
riscv-tests/isa/macros/simplev/sv_test_macros.h and anything starting
isa/rv*/sv*.c

 the table that i created here:
https://libre-riscv.org/simple_v_extension/opcodes/

 basically that very early preliminary work i did on some unit tests
needs a "category" macro that will allow *every* operation within a
particular category to be tested for:

 * scalar-scalar (SV=off)
 * scalar-scalar (VL=1)
 * scalar-vector
 * vector-scalar
 * vector-vector
 * predicated permutations of all of the above
 * zero-predicated permutations of all of the above
 * *inverted* predicated permutations of all of the above

all of these will produce a really quite massive matrix of tests:
that's just how it will go.

if you take a peek at sv_addi_predicated.S you can see i've made a
start on that... however if you look at rv64ui/addi.S, and track down
TEST_IMM_OP to isa/macros/scalar/test_macros.h, *that's* more like
what is needed: the macro in sv_addi_predicated.S being able to
actually pass in the *instruction* to be tested, along with the
starting data and expected answer.

it's quite a big task, now that i think about it, hence the need for some help!

the thing is, you'll get a good familiarity with RISC-V assembly and
instruction format, pretty quickly, which is probably something that,
as a hardware designer, you'd want to do anyway.  however if you get
totally bored with it after a while, that's fine, there's plenty other
things to do.

l.