[libre-riscv-dev] maybe adding OmniXtend support

Jacob Lifshay programmerjake at gmail.com
Wed Dec 19 10:49:10 GMT 2018

Western Digital is working on creating OmniXtend, which is basically
TileLink with modifications over ethernet:

https://youtu.be/qQnpF8pbuAU starting at 16:05

I think implementing support for it in the Libre SoC is a good idea
(assuming that we are going to have ethernet anyway) as it makes for a easy
way to connect to external parts using a cache-coherent protocol and it
shouldn't take that much additional area or power.

One of the most important parts is that it can leverage already existing
ethernet PHYs and switches, so those won't have to be reimplemented.

>From what I read in the spec, TileLink is about as simple as you can get
for a extendible cache-coherent protocol with fast at-memory atomic rmw

I think supporting OmniXtend will make our SoC really useful for
implementing large low-cost shared-memory systems and will be really useful
for things like low-cost many-core servers (4 cores per chip at $4 per chip
+ ram + ethernet switch chips + power + PCB; I have not done any research,
but it sounds really inexpensive) and for crypto-miners.

One other benefit is that we don't need additional i/o pins to support it.
I haven't checked, but we may also be able to run tcp/ip over the same port
simultaneously without worrying about security since the protocol number
would be different than IP.

Jacob Lifshay

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