[libre-riscv-dev] GPU design

Luke Kenneth Casson Leighton lkcl at lkcl.net
Mon Dec 10 16:45:11 GMT 2018

On Mon, Dec 10, 2018 at 2:45 PM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:

> > so, the instruction sequence number needs to be the means of
> > prioritising the regfile 4-way multiplexers.  lowest (oldest)
> > sequential number always wins, and in this way i believe we may ensure
> > that even with up to 4 instructions completing at once, the commit
> > order is always preserved.
> >
> > it may be more complex than that, now that i think about it.
> it's both less complex and more involved.  we definitely need to do a
> simulation.


 so there's a link to the original video in the description.  the key
additions and changes are:

* the reservation stations of the original video are "flattened", and
given *separate* Function Unit identities, even though they actually
go to the same ALU.
* a "Dependency" bit in the matrix which preserves the instruction
execution order.  this is directly equivalent to the Reorder Buffer
"head of queue" pointer.  it prevents "commit", and may be used for
precise exceptions as well as branch speculation.

other than that, there really is nothing special / extra.

really really need to write a simulator for this.


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