[libre-riscv-dev] GPU design

Jacob Lifshay programmerjake at gmail.com
Sun Dec 9 21:15:50 GMT 2018

On Sun, Dec 9, 2018, 05:34 Luke Kenneth Casson Leighton <lkcl at lkcl.net

> On Sun, Dec 9, 2018 at 12:09 PM Jacob Lifshay <programmerjake at gmail.com>
> wrote:
> > I still think it's a good idea to build the prototype register allocator,
> > but targeting the split reg file, to get the algorithms worked out before
> > getting into the complexity of existing code in llvm.
>  do you mean the "renaming" mechanism? or the multiplexor?  or the
> Reservation Stations... or all of the above? :)
I don't mean any of the hw used to implement it, i mean the part of a
compiler that allocates architecturally-visible registers for variables. SV
is unusual in that it will need a 2-pass register allocation algorithm:
allocating each variable a range of successive registers from the 128 SV
rename target registers, then allocating the registers used in the actual
instruction encodings and adding csr writes wherever they are needed.

Note that I think it will be very important that we are able to write to a
csr to change the rename cam and be able to use the new rename entry with
the vectorized instruction able to start in the clock cycle immediately
after the previous vectorized instruction starts, either through macro-op
fusion or dual-issue or some other means. We may want to add additional
instructions that allow programming the rename table faster than the
builtin csr instructions. I would suggest a csrrwi with a bigger immediate
and a smaller csr selector.


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