[libre-riscv-dev] 3d gpu microarchitectural requirements review

Luke Kenneth Casson Leighton lkcl at lkcl.net
Sun Dec 2 06:50:38 GMT 2018

i've been thinking about this for several weeks, and in light of
review and discussion on comp.arch i can see that there is a case for
having a multi-issue microarchitecture with register renaming, rather
than a greatly simplified SIMD-with-predication engine.

the first and simplest reason is: non-vectorised performance improves
dramatically as well, and if ZOLC [1] is deployed we would get
near-100% pipeline fill with absolutely no need for branch prediction,
on multimedia workloads.

if we are to stick with a predicated-SIMD microarchitecture it will be
necessary to work out how to deal with register overlaps.  we have an
advantage in SV in that the overlapping registers actually map down to
"real" registers.

lots to think about.


[1] https://www.researchgate.net/publication/3351728_Zero-overhead_loop_controller_that_implements_multimedia_algorithms

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