[Libre-soc-isa] [Bug 1243] when loading index registers, have defined behavior for out of range indexes

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1243

--- Comment #6 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #4)
> comparators against -1 are likewise not a good idea.

a comparison against -1 takes less latency than the addition that indexing mode
already has to do anyway. a comparison would have the latency of an 8-input
and-gate, which is comparable to a 2-bit adder, and we need at least a 7-bit
adder either way.

remember all those can be done in parallel. the only additional latency is that
of 1 layer of nand or nor gates (depending on what register number the zero
register is given), or can be merged into the final layer of xor gates for the
sum output, giving essentially zero additional latency.

alternatively, instead of having a zero register, it could just change that
input/output to use r0, which might be even more powerful since it allows
loading zero for compatibility, as well as any other value you want to stuff in
r0. additionally, this alternative only requires 7-bit register numbers instead
of kinda 8-bit.

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