[Libre-soc-isa] [Bug 1071] add parallel prefix sum remap mode

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1071

--- Comment #27 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
ok, so jacob, you need to examine the registers in and out on all
of the sv management instructions, and memorise them, and start to
understand - and accept - fully, the consequences for implementability.

* setvl has GPR in, GPR out, SVSTATE in and out, and CTR in and out.
  both SVSTATE and CTR are "state" at the same peer level
  as PC and MSR so are exceptional: they are not entirely
  normal Hazards (just like PC is not a norml hazard).
  *and* Rc=1.

  *SEVEN* registers. that's insane.

  some implementations will just have a hard time keeping
  the IPC to 1, here. it is what it is.

* svstep is GPR out and SVSTATE in and out (i added GPR in
  recently but will likely back it out) *and* Rc=1

* with the exception of svindex the REMAP instructions are ONLY
  modifying "state" at the level of PC and MSR: SVSTATE and SVSHAPE*.

svindex had to have some very special conditions placed on it to
not cause catastrophic damage to implementability (read the spec on
this please).

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