[Libre-soc-isa] [Bug 1161] EXTRA2/3 algorithm likely inconsistent with EXTRA2 tables causing PowerDecoder2 and insndb to disagree on scalar EXTRA2 register encoding for >=r32

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1161

--- Comment #7 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #6)
> an additional unit test suite is needed which puts register values in
> to high numbers then say "adds one" to each (sv.addi r80, r80,1) with
> say VL=4, and checks that they all are correctly updated.

ok, that should be doable...

> a set of instructions will have to be selected which cover all 5
> categories: NORMAL CROPS BRANCH LDST_IMM LDST_IDX

we'll probably also want FP insns. we'll need a representative example
instruction for each category, that insn also needs to have the properties
necessary for easy testing of all input/output register fields (hence why I
picked maddedu rather than isel, since isel doesn't copy the condition input to
any output (so we can check that the input pattern is in the output reg),
making it easier to end up with a unit test that passes even though the insn is
broken.)
> 
> this will need to be ISACaller/HDL unit tests rather than asm/disasm
> tests of binutils.

the unit tests I already wrote should do that, they just need to be extended to
the additional insns and VL=4.

https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/test/svp64/encodings.py;h=d5bf476c7fd036889767d0d140afa3030f908c48;hb=cce08ed213d1de4d2f11b493917e1c34f9c40b61

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