[Libre-soc-isa] [Bug 1161] EXTRA2/3 algorithm likely inconsistent with EXTRA2 tables causing PowerDecoder2 and insndb to disagree on scalar EXTRA2 register encoding for >=r32

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Sun Sep 17 13:06:22 BST 2023


https://bugs.libre-soc.org/show_bug.cgi?id=1161

--- Comment #5 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
jacob i've now had the opportunity to think about this (which was
needed in my own time and *before* any modifications are made).

the use of the intermediate variable "extra" is there to make the
spec easier to read. please preserve it. use the following strategy:

if EXTRA3:  # EXTRA3 scalar is EEnnnnn vector is nnnnnEE
  extra = spec[1:2]
elif isvec: # EXTRA2 vector gives r0-126 in steps of 2 nnnnnE0
  extra = spec[2] << 1
else        # EXTRA2 scalar gives range r0-r63 0Ennnnnn
  extra = spec[2]

# now with the difference between EXTRA2 and EXTRA3 removed
# all that is left is to detect vec/scalar
if isvec: SVregnum = regnum<<2 | extra
else      SVregnum = regnum    | extra<<5

this will need adapting for CR-with-SV.

you will need to find *all* locations where the above algorithm
needs to be placed. please find them and put the corrections into
a branch, and also update the PowerDecoder2 variant to match the
above so that anyone reading the spec and the source code can
see clearly that they are related.

-- 
You are receiving this mail because:
You are on the CC list for the bug.


More information about the Libre-SOC-ISA mailing list