[Libre-soc-isa] [Bug 1161] EXTRA2/3 algorithm likely inconsistent with EXTRA2 tables causing PowerDecoder2 and insndb to disagree on scalar EXTRA2 register encoding for >=r32

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1161

Jacob Lifshay <programmerjake at gmail.com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|CONFIRMED                   |IN_PROGRESS

--- Comment #3 from Jacob Lifshay <programmerjake at gmail.com> ---
I added some tests to see if the assembler(s) match the simulator.

I then fixed PowerDecoder2 and the algorithms on the wiki. now the 256-bit mul
and the new tests I just added pass!

If someone can double check the changes to the wiki, I'd greatly appreciate
that -- that's all that's left for this bug

https://git.libre-soc.org/?p=libreriscv.git;a=commitdiff;h=24576f370d5b0b0282b821062c66e1ff39ab8019

commit 24576f370d5b0b0282b821062c66e1ff39ab8019
Author: Jacob Lifshay <programmerjake at gmail.com>
Date:   Fri Sep 15 14:47:00 2023 -0700

    fix scalar EXTRA2 in EXTRA2/3 decoding algorithms

https://git.libre-soc.org/?p=openpower-isa.git;a=shortlog;h=630dfa6c8b6633d66d1a41368dfad927754846ed

commit 630dfa6c8b6633d66d1a41368dfad927754846ed
Author: Jacob Lifshay <programmerjake at gmail.com>
Date:   Fri Sep 15 14:21:00 2023 -0700

    fix PowerDecoder2 to properly decode scalar EXTRA2

    https://bugs.libre-soc.org/show_bug.cgi?id=1161

commit cce08ed213d1de4d2f11b493917e1c34f9c40b61
Author: Jacob Lifshay <programmerjake at gmail.com>
Date:   Fri Sep 15 14:20:09 2023 -0700

    add tests for checking if the simulator and assembler agree on SVP64
encodings

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