[Libre-soc-isa] [Bug 1055] update ls004 OPF RFC to include LD-ST-Shifted instructions

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1055

--- Comment #10 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
ARM register offset load/store word and unsigned byte instructions.

https://developer.arm.com/documentation/ddi0406/c/Application-Level-Architecture/Instruction-Details/Shifts-applied-to-a-register/Constant-shifts


LDRSB  R0, [R5, R1, LSL #1] ; Read byte value from an address equal to
                             ; sum of R5 and two times R1, sign extended it

https://developer.arm.com/documentation/dui0552/a/the-cortex-m3-instruction-set/memory-access-instructions/ldr-and-str--register-offset

added first cut of loadstoreshift.mdwn page
https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=5990036b5

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